Full functionality testing is known to be carried out on semiconductor solder bump connect dies while the dies are still embodied in the silicon wafer. However, burn-in followed by the testing of semiconductor wire bond dies is generally not done at the wafer level because of inherent structural difficulties and the nature of making wire connections to external structures. Instead, burn-in and full testing of wire bond dies is generally done only after the dies have been severed from the wafer and packaged.
Typically, semiconductor wire bond dies defined on a semiconductor wafer undergo initial low-level dc testing wherein individual dies are tested for satisfactory operation. However, there are problems associated with this form of testing. External testing probes directly contacting wire bond pads can damage the wire bond pads by scratching or marking the pads such that subsequent wire bond electrical connection thereto can be difficult. In addition, electrical contact to wire bond pads may be inconsistent when probe contacts must be maintained for any considerable length of time.
After dc testing, the wafer is severed between individual dies, inoperable dies are discarded, and operable dies are collected for packaging into a module. After packaging, burn-in and full functionality testing of each die circuit is conducted under extended time and temperature conditions directed to assessing circuit reliability. If a particular wire bond die is found inoperable after packaging, the entire module must often be discarded.
Efforts have been made to eliminate the need for two separate tests and to avoid damaging the surface of the wire bond pad. Such efforts have principally been directed toward constructing a method and structure for conducting wafer level burn-in and full functionality testing of wire bond dies. However, these methods generally require use of additional test structures and levels of interconnection in the kerf region of the wafer. Such structures typically must be removed before dicing the die from the wafer in order to prevent degradation of internal die circuitry performance. Another problem associated with the use of test structures formed in the kerf region is that the number of dies which can be defined on a wafer is limited by the amount of area the test structures require. In addition, the technology required for adding and removing temporary interconnections can contribute significantly to the wafer processing costs.
A need, therefore, continues to exist for an improved structure and method for achieving burn-in and full functionality testing of a semiconductor wire bond die.